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Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Two LVCMOS outputs @ 3.3V, 17 typical output impedance * Selectable crystal oscillator interface or LVCMOS single-ended input * Output frequency range: 46.66MHz - 233.33MHz * VCO range: 560MHz - 700MHz * Supports the following output frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz * RMS phase jitter @ 212.5MHz (637KHz - 10MHz): 0.83ps (typical) Typical phase noise at 212.5MHz: Offset Noise Power 100Hz ............... -91.3 dBc/Hz 1KHz .............. -114.3 dBc/Hz 10KHz .............. -120.7 dBc/Hz 100KHz .............. -120.2 dBc/Hz * Full 3.3V or 3.3V core/2.5V output supply modes * 0C to 70C ambient operating temperature * Lead-Free package RoHS compliant
GENERAL DESCRIPTION
The ICS840002 is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The ICS840002 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840002 is packaged in a 16-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 F_SEL1 0 0 1 1 0
FOR
FIBRE CHANNEL APPLICATIONS
Inputs M Divider Value 24 24 24 24 24 N Divider Value 3 4 6 12 4 M/N Ratio Value 8 6 4 2 6 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25
F_SEL0 0 1 0 1 1
BLOCK DIAGRAM
OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown
PIN ASSIGNMENT
2
F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT
XTAL_IN 26.5625MHz
OSC
XTAL_OUT TEST_CLK Pulldown
0
F_SEL1:0
1 Phase Detector
00 01 10 11
1
VCO
0
N /3 /4 /6 /12 (default)
ICS840002
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
Q1
M = /24 (fixed)
MR
840002AG
Pulldown
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REV. A MARCH 11, 2005
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Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Input Input Input Input Input Pullup Pulldown Pulldown Pullup Pulldown Description Frequency select pin. LVCMOS/LVTTL interface levels. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/n output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Cr ystal oscillator interface. Output supply pin. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power supply ground. Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 Name F_SEL0 nXTAL_SEL TEST_CLK OE MR
6 7 8 9, 10 11 12, 13 14, 15 16
nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN VDDO Q1, Q0 GND F_SEL1
Input Power Power Input Power Output Power Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance 3.3V5% 2.5V5% 14 16 Test Conditions Minimum Typical 4 8 51 51 17 21 21 25 Maximum Units pF pF k k
TABLE 3. FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 F_SEL1 0 0 1 1 0 F_SEL0 0 1 0 1 1 Inputs M Divider Value N Divider Value 24 3 24 24 24 24 4 6 12 4 M/N Divider Value 8 6 4 2 6 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25
840002AG
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REV. A MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 100 12 5 Units V V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter VIH Input High Voltage Input Low Voltage Input High Current Input Low Current F_SEL1:0, nPLL_SEL, nXTAL_SEL, OE, MR TEST_CLK F_SEL1:0, nPLL_SEL, nXTAL_SEL, OE, MR TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.3V 5% VDDO = 2.5V 5% VDDO = 3.3V or 2.5V 5% -150 -5 2.6 1.8 0.5 Test Conditions Minimum Typical 2 2 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V V
VIL
IIH
IIL VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pf parallel resonant crystal.
840002AG www.icst.com/products/hiperclocks.html REV. A MARCH 11, 2005
Test Conditions
Minimum
Typical 26.5625
Maximum
Units MHz
Fundamental 50 7 pF
3
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.67 170 113.33 56.67 12 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 0.83 0.62 0.59 0.80 0.68 200 700 54 58 Units MHz MHz MHz MH z ps ps ps ps ps ps ps % %
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF
Output Rise/Fall Time
F_SEL[1:0] 00 46 odc Output Duty Cycle F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency Range F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.67 170 113.33 56.67 12 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 0.73 0.62 0.56 0.76 0.72 200 700 54 58 Units MHz MHz MH z MH z ps ps ps ps ps ps ps % %
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF
Output Rise/Fall Time
F_SEL[1:0] 00 46 odc Output Duty Cycle F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840002AG
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REV. A MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
0 -10 -20 -30 -40 -50
Fibre Channel Filter 53.125MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 0.68ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE AT 212.5MHZ @3.3V
0 -10 -20 -30 -40 -50
Fibre Channel Filter 212.5MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 0.83ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -160 -170 -180 -190 100 1k 10k 100k
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel to raw data
1M 10M 100M
-150
OFFSET FREQUENCY (HZ)
840002AG www.icst.com/products/hiperclocks.html REV. A MARCH 11, 2005
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Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
V
Qx
DDO
2
Phase Noise Mask
V
Qy
DDO
2 tsk(o)
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT SKEW
V
80% 20% tR
80%
Q0, Q1
DDO
2 Pulse Width t
PERIOD
Clock Outputs
20% tF
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
840002AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840002 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840002
Figure 2. CRYSTAL INPUt INTERFACE
840002AG
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REV. A MARCH 11, 2005
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Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins.
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840002. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install VDD
R2 33
Zo = 50 Ohm
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
U1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Zo = 50 Ohm C5 0.1u XTAL2 R4 100
LVCMOS
VDD R1 10
VDDA C3 10uF C4 0.01u C6 0.1u
FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD
FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT
VDD R3 100
ICS840002
If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground.
LVCMOS C2 22pF X1 XTAL1
Optional Termination
C1 22pF
Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated.
FIGURE 3. ICS840002 SCHEMATIC EXAMPLE
840002AG
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REV. A MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
137.1C/W 89.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840002 is: 3085
840002AG
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REV. A MARCH 11, 2005
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Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
16 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
840002AG
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REV. A MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS840002
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS840002AG ICS840002AGT ICS840002AGLF ICS840002AGLFT Marking ICS840002AG ICS840002AG TBD TBD Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AG www.icst.com/products/hiperclocks.html REV. A MARCH 11, 2005
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